PMNet Packet processing
Packet processing pipeline for PMNet implemented in P4 language. PMNet packet processing manipulates incoming network packets and generates control signal for the Datapath in FPGA.
- Vivado 2018.2
- Xilinx P4-SDNet toolchain (available through Xilinx University Program)
Bugs and limitations
- P4 module for Cache response generation is buggy: a temporary fix will only respond read requests from the same client that sends the update.